This invention relates to the field of electronic circuits. More particularly, this invention relates to an electronic circuit capable of generating a relatively long delay period and that can be incorporated into a CMOS integrated circuit using a small amount of chip area.
In integrated circuit digital design it is often desirable to generate a delay period or a timing pulse that is relatively very long when compared to the system clock signal used in the circuit. For example, digital CMOS circuits typically operate with system clocks measured in nanoseconds (ns). In some applications, it is desirable in such circuits to generate a delay which may be very long compared to the nanosecond clock rate, for example, a delay of several tens to several hundred milliseconds (ms). One application for such a delay may be in chip power up, where a chip, after power up, must delay any output signals it sends to other chips in the computer system so that it can be sure the other chips have had sufficient time to completely power up. Such a delay in a typical system might be 100 ms. If the chip's system clock is 10 ns, the desired delay of 100 ms will be 10,000,000 clock cycles.
Two known methods for generating such a large delay have proven particularly disadvantageous when applied to circuits fabricated with standard CMOS technology. One such method is the use of a counter circuit. Counter circuits have disadvantages in that the amount of delay they can generate is strictly limited by the size of the counter circuit and the clock driving the counter. For example, a 16 bit counter circuit operating in an electronic circuit that uses a clock of 10 ns could generate a maximum delay pulse of 2.sup.16 times 10 ns or 0.65 ms. Such a 16 bit counter bit circuit uses a relatively large amount of circuit layout area.
The second known method for generating a long delay pulse is the use of RC delay circuit. Fabrication of such a circuit using standard CMOS technology creates a problem in that the RC circuits require a very large resistor in order generate a delay pulse of sufficient length. This large resistor may be on the order of several tens to several hundred megaohms. The only practical way to manufacture such a large resistor in CMOS technology is to use large n well resistors, which require a large layout area. Use of large n well resistors also requires care to prevent parasitic transistors from forming between the large n well areas.
What is needed is an electronic circuit suitable for fabrication with CMOS technology capable of generating a delay pulse that is relatively long when compared to the clock frequency of the circuit and that uses a minimum of circuit layout area.